There is a demand to increase data rates of signal transmission and signal reception inside and outside a device as performance improvement of an information processing apparatus such as a communication-based device or a server. For example, a bit rate is desired to be further heightened, in the field of high-speed I/O that transmits and receives a signal in an integrated circuit chip or between chips (in a device or between devices), or in the field of optical communication.
In a reception circuit, there is a demand to determine the transmitted data at an appropriate timing, and to recover data and clock (clock and data recovery: CDR). CDR is realized by detecting a phase difference and a frequency difference between the input data and the received (sampling) clock, and performing phase adjustment of the sampling clock based on information thereof. Known is a CDR circuit that performs retiming by a clock recovered from input data without using a reference clock even in the reception circuit, and outputs data of which jitter is decreased.
In the CDR circuit, it is known to use a phase detection circuit (phase detector: PD) that detects the phase difference between the input data and the clock. Based on the phase difference detected by the phase detection circuit, the phases and the frequencies of the input data and a first clock are controlled to be matched. A state where the frequencies thereof are matched is referred to as a lock state. Here, a state that is not the lock state is referred to as a non-lock state.
However, the phase detection circuit has problems that a frequency range in which clock recovery is possible is narrow, and it is not possible to detect a change to the non-lock state from the lock state.
The followings are reference documents.
[Document 1] Japanese Laid-open Patent Publication No. 2011-135149, and
[Document 2] Ansgar Pottbacker, et al., “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s”, IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, December 1992.